Technical Talk by Keynote Speakers

The conference itinerary includes a diverse array of technical events geared towards societal advancement under the auspices of the IEEE Society. Key highlights of the event encompass a series of technical talks featuring contributions from four esteemed keynote speakers actively engaged in technological advancements:

Keynote Speakers:

Mr. Venu Pakalapaty, Director of Engineering at Qualcomm, leads the Machine/Deep Learning chip design group. His primary focus is Hardware Intellectual Property (IP) development, ASIC System design that fits into Snapdragon (trademark) SOCs.

Over the past 2+ decades Industry experience, Venu worked extensively on niche technologies such as Wireless modems (3G/4G/5G), WLAN (802.11ac/ax), Global Navigation, Wired networking (IP/ATM)

In the recent years, Venu primary focus was in Artificial Intelligence (ML/DL) based ASIC designs, spec to silicon for product across Mobile, Compute, IOT, XR, Tablets and Auto.

Venu holds 7 granted patents and few more in the counting. Venu holds a Masters' degree in Engineering from Indian Institute of Science, Bangalore.

Title of the Talk: "Next generation Cores & Technologies and the VLSI challenges and opportunities"


User expectations, demands, experience from Digital Devices and services are undergoing phenomenal change. This causes applications to run workloads that have varying processing needs. To meet this goal, processing is becoming more heterogeneous. In this keynote address we will take a look at reasons why processing is becoming Heterogeneous and evolution of Heterogeneous processing elements like CPU, GPU, NPU, TPU and their Trends.

This key-note attempts to share some insights into IP/Cores and how they serve as the foundation to great product making. It also gives a quick sneak peak into various use cases -- current and future technology trends. While academia focusses on Open ended Research, Industry focuses on practically realizable solutions and Chip design is a important piece in this whole thing. VLSI domain has clearly evolved over the decades, but there are new challenges and opportunities that lie ahead of us which will also be the focus of this talk.

Keynote Speaker-1

Keynote Speaker-2

Title of the Talk: "Heterogeneous Computing Trends"

Mr. Madhusudan Sampath is one of the top semiconductor industry leader. He is expertise in high performance ASIC/FPGA and SoC based product architecture, design, verification and validation. He is pioneer in setting up and leading high performance team from the scratch to deliver world class semiconductor system solutions. He is specialized in End to End Project Life Cycle Management, Design Thinking, Emerging Memories, Video processing, Solid state storage, VLSI, ASIC, SOC, Embedded and FPGA based products & solutions.

Madhusudan has over 25 years of reach industry experience. He has worked in companies like Micron Technology, Mind Tree, Co-Founder or RiverSilica Technologies Pvt Ltd, etc. He is Senior IEEE member. Currently, he is Director & Group Head, SoC & System IP. Samsung Semiconductor India R&D


Director & Group Head, SoC & System IP, Samsung Semiconductor India R&D.

Director of Engineering at Qualcomm, Machine/Deep Learning chip design group lead.

Dr. Prem Singh is co-founder and Director of Mantiswave Networks Pvt. Ltd., a start-up in the 5G wireless communication domain and a faculty member at IIIT Bangalore. Previously, he worked as Project Executive Officer on the Indigenous 5G Testbed project, where he designed FPGA based hardware, and software algorithms for an end-to-end 3GPP compliant 5G-NR Testbed. He received the M. Tech and PhD degrees in Electrical Engineering from the Indian Institute of Technology Kanpur, India. His PhD thesis received the Best Thesis award in IEEE CICT 2020 organized by IIIT Kancheepuram, India, and he was also one of the finalists (top two) for the Indian National Academy of Engineering (INAE) Innovative Student Project Award 2021. His current research interests lie in the area of embedded system design for 5G and beyond wireless systems including FPGA based hardware design, 3GPP compliant firmware design, Private 5G and Testbed setup. His research interests also include Transceiver design for 5G and beyond wireless systems including parameter estimation, Orthogonal Time-Frequency space (OTFS), and ML applications for 5G and beyond wireless system design. His two recent research papers were picked by the IEEE Communication Society for the best readings for OTFS and Delay-Doppler signal processing. His student’s paper was one of the finalists for the best student paper award at the IEEE SPCOM 2022, held at IISc Bangalore.

Title of the Talk: "Accelerator Card Design for Open RAN and 3GPP Compliant Distributed Unit for 5G"

With the rapid evolution of telecommunications networks towards open, disaggregated architectures, the Open Radio Access Network (ORAN) paradigm has emerged as a transformative approach. Within this framework, the Distributed Unit (DU) plays a pivotal role in processing and managing radio access functions. To meet the increasing demands for data throughput, low latency, and scalability, integrating accelerator cards into ORAN DUs has gained significant attention. By offloading compute-intensive functions such as forward error correction coding, rate matching, scrambling etc, and machine learning inference, accelerator cards enhance the overall performance and efficiency of ORAN deployments. This talk presents an overview of design and integration of FPGA based accelerator card into ORAN DUs and explores the ensuing benefits.

Keynote Speaker-3


Co-founder and Director of Mantiswave Networks Pvt. Ltd.

Mr. Ayan Datta has  over 15 years of experience in the VLSI industry, he's held pivotal roles at industry giants, contributing significantly to digital circuit design and innovation. He currently leads the design enablement team at Western Digital, shaping methodologies for next-gen ASICs and evaluating emerging technology nodes. Previously, he spearheaded digital circuit design for microprocessor cores on cutting-edge sub-micron technology at Intel. Prior to Intel, he directed the Common Library Design Team at IBM, managing designs for both P and Z processor lines, balancing divergent specifications and execution challenges. His expertise spans semi-custom digital circuit design, VHDL synthesis, physical design, and IP placements, addressing high-performance frequency and stringent power constraints. Beyond execution, he's actively involved in refining methodologies and architecting solutions for multi-usage projects. Additionally, he's passionate about 3D ICs, reliability issues in digital designs, and Engineering Change Order processes. His journey began as a lecturer, where he imparted knowledge on digital and VLSI design, laying the foundation for his subsequent industry leadership roles. Throughout his career, he's been recognised for performance excellence and has accumulated over 6 US patents and 7 publications in leading IEEE conferences and journals.

Title of the Talk: "Gen-erational Transformation in VLSI Design in the Era of Gen AI"

Keynote Speaker-4


Technologist at Western Digital, Chair IEEE CAS Bangalore Chapter. IEEE Senior Member