Workshop and Tutorial are happening in a hybrid online and offline mode

Tutorial- 1

Tutorial Title: Challenges of Digital Design Verification

Abstract: It is estimated that 50% to 70% of the engineering resources in a chip design company are spent on design verification. Writing testbenches, Simulation and debugging, Writing and running assertions, estimating and improving functional coverage, running regression tests and debugging constitute the activities of design verification engineers. System Verilog, along with Universal Verification Methodology, has gained traction in the industry for verification of large and complex digital designs. The purpose of this hands-on tutorial is to expose the participants to the above concepts in design verification. The tutorial will also bring out why artificial intelligence and machine learning are being explored in tasks such as achieving functional coverage closure. It is assumed that participants have taken a course in digital design and have a working knowledge of Verilog or VHDL. Candidates must bring their own laptop and must have access to Internet.

Brief profile of organizer:

C.P. Ravikumar is the Chief Learning Officer at Vinyana Tech, Bangalore. He is an Adjunct Professor

at IIT Madras and IIIT, Dharwad. Earlier, he has served as the Director of Technical Talent
Development at TI (India), as Vice President (Training) at Control Net India and as Professor of
Electrical Engineering at IIT Delhi.

Ravikumar obtained a Ph.D. in Computer Engineering from the Department of EE-Systems at University of Southern California (1991). He obtained an M.E. in Computer Science from Indian Institute of Science (1987) with highest scores and a B.E. in Electronics from Bangalore University (U.V.C.E.,1983) with a Gold Medal for highest scores. He has published over 250 research papers in the areas of VLSI physical design, VLSI test, parallel processing, electronic design automation and embedded systems in peer-reviewed journals and conferences. He has won four best-paper awards in international conferences of the IEEE and one best paper award in the IETE Journal of Education. He is the author/coauthor/editor of 15 books in the areas of VLSI design and Embedded Systems. He holds 4 US patents in the area of VLSI Test. He is a Fellow of INAE and a senior member of IEEE.

He founded the IEEE CAS Bangalore Chapter and has served as its honorary secretary. He has served as the honorary secretary of VLSI Society of India for 8 years. He established the VLSI Design Test and Symposium (VDAT) in India and was the general chair of this event for 15 years. He has served on the committees of numerous conferences in various capacities such as Program Chair and General Chair. He has served on the editorial committees of several journals, including Journal of Electronic Testing – Theory and Applications (Springer) and Journal of Low Power Electronics (ASP). He has received an award from Zinnov foundation and a recognition from IESA for his work with Indian universities. He received the “Best Blogger” award from TI University Program (2014).

Tutorial- 2

Tutorial Title: "Physical Verification and Validation of Digital Analog and Mixed-Signal Designs for SCL 180nm CMOS Technology"

Abstract:

Physical Verification and Validation of Digital Analog and Mixed-Signal Designs for SCL 180nm CMOS Technology: Procedures prior to physical verification for the designs using SCL 180nm Process: Silicon number placement, Seal-ring insertion & guidelines, IO Pad pitch requirements, Dummy cells placement, Usage of clock pads and powering up the chip in SCL 180nm process, IO pad ring establishment with and without cut-cells, Physical verification, Design Rule Checks (DRCs), Antenna Design Rule Checks, Layout vs Schematic (LVS), Parasitic extraction, Spice simulations closure for all PVT (Process, Voltage, Temperature) variations, Tapeout sign-off and submission, Packaging requirements, bond pad and bond wire rules, bonding diagram, checklist, etc.

Brief profile of organizer(s):

Leya Wels is a Project Engineer at C-DAC Bangalore, currently associated with the Secure Hardware and VLSI Design group. She possesses two years of industry experience and holds a Bachelor of Technology degree in Electronics and Communication Engineering from Rajagiri School of Engineering & Technology, Kochi. Her work has primarily focused on the automation of physical verification and validation processes for digital, analog, and mixed-signal designs targeting the SCL 180nm CMOS technology node. Additionally, she is involved in the physical design of digital IP cores.

Pranose J. Edavoor received the Bachelor’s degree in Electronics and Communication Engineering from Cochin University of Science and Technology, Kerala, India, in 2012, the Master’s degree in Very Large-Scale Integration (VLSI) from the National Institute of Technology Goa, India, in 2016, and the Ph.D. degree in Electrical and Electronics Engineering from the same institute in 2021. He is currently with the Centre for Development of Advanced Computing (C-DAC), Bangalore, where he is involved in the design and development of AI accelerators and RISC-V-based processor architectures. His research interests include digital design, FPGA and ASIC-based accelerators, processor architecture, wavelet transforms, and deep neural networks.

Workshop- 1

Tutorial Title: "Designing Low-Dropout Regulations: Fundamentals to Advanced Techniques "

Abstract:

Many mixed-signal systems use low-dropout (LDO) regulators to provide dedicated supply rails for each functional block. By isolating circuits from both global VDD noise and each other’s switching disturbances, LDOs preserve signal integrity. However, they require minimal input-output voltage differentials for maintaining the efficiency. Thus, LDOs are typically paired with switching converters like buck regulators for coarse voltage step-down, with LDOs filtering residual noise arising due to switching activity. LDO design involves inherent trade-offs like high power supply rejection ratio (PSRR) compromises transient speed, and vice versa. This tutorial derives core LDO topology from first principles through intuitive circuit analysis, avoiding heavy formalism. Two detailed design case studies of a high-PSRR LDO for noise-sensitive RF systems, and a fast-transient LDO for digital loads will be discussed. These will include the respective Cadence and MATLAB simulations. The latter half examines capacitor-less LDO architectures such as Flipped Voltage Follower (FVF), and Domino-like Buffered topologies, eliminating the need for off-chip capacitors without significant degradation in the performance. Recent case studies from JSSC, TCAS-I, and TPEL publications will be discussed to familiarize participants with state-of-the-art techniques.

Brief profile of organizer(s):

Soham Lakhote received his B.Tech degree in Electronics and Telecommunication Engineering (EXTC) from Veermata Jijabai Technological Institute (VJTI), Mumbai, in 2019. He is currently a final-year Ph.D. candidate working under Prof. Gaurab Banerjee in the Department of Electrical CommunicationEngineering (ECE) at the Indian Institute of Science (IISc), Bangalore, where he achieved a CGPA of 9.4

in his coursework.

His research focuses on the development of interference-tolerant FMCW Radar-on-Chip systems for vital signs detection, with a particular emphasis on characterizing and mitigating hardware non-idealities and evaluating their impact on system-level radar performance. His areas of expertise include Analog and RF Circuit Design, Chip Characterization, FMCW Radars, and Communication System Design.

Soham has been recognized with the prestigious Prime Minister’s Research Fellowship (PMRF) for his academic excellence and research contributions. He was also awarded the Best Paper Award at the IEEE AISP 2022 Conference. Additionally, he has been a topper in three NPTEL courses: Analog Electronics, Digital VLSI Design, and Phase-Locked Loops. Beyond his academic pursuits, he currently serves as the Chapter Chair of the IEEE-IISc VLSI Student Branch Chapter, leading a dynamic team of 12 members. He is also an upcoming intern at Qualcomm’s Systems Engineering team.

Rahul Reji is a final year M.Tech student at IISc Bangalore working under Prof. Chetan Singh Thakur and specializing in neuromorphic circuits. He obtained his B.Tech degree from the National Institute of Technology Karnataka, Surathkal in 2021. Before joining IISc, he was working as a Digital Design Engineer at Texas Instruments. Rahul is passionate about creating electronic systems that significantly improve everyday life.

Koteswar Doddi completed his B.Tech. (Hons.) in Electronics and Telecommunication Engineering (E&TC) from the Indian Institute of Engineering Science and Technology, Shibpur (IIESTS), West Bengal in the Year 2021, and thereafter joined IISc to pursue PhD. During his coursework, he did an internship at STARC (a Unit of SITAR), Bangalore, for developing a mathematical model (focussed on MEMS photolithographic processes) for the industrial cantilever structures using the Coventor-ware software in 2019. This was followed by another internship at Synopsys, Inc, Bangalore in the domain of firmware developing Perl parsers, and RTL Codes for the SERDES (Serializer/ Deserializer) system in the year 2021. His primary research interests include analog and mixed-signal integrated circuits and systems Design, PCB prototyping, 2D materials-based device fabrication and modeling.

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