Tutorial-1
Tutorial Title: Challenges of Digital Design Verification
Abstract: It is estimated that 50% to 70% of the engineering resources in a chip design company are spent on design verification. Writing testbenches, Simulation and debugging, Writing and running assertions, estimating and improving functional coverage, running regression tests and debugging constitute the activities of design verification engineers. System Verilog, along with Universal Verification Methodology, has gained traction in the industry for verification of large and complex digital designs. The purpose of this hands-on tutorial is to expose the participants to the above concepts in design verification. The tutorial will also bring out why artificial intelligence and machine learning are being explored in tasks such as achieving functional coverage closure. It is assumed that participants have taken a course in digital design and have a working knowledge of Verilog or VHDL. Candidates must bring their own laptop and must have access to Internet.
Brief profile of organizer:
C.P. Ravikumar is the Chief Learning Officer at Vinyana Tech, Bangalore. He is an Adjunct Professor
at IIT Madras and IIIT, Dharwad. Earlier, he has served as the Director of Technical Talent
Development at TI (India), as Vice President (Training) at Control Net India and as Professor of
Electrical Engineering at IIT Delhi.
Ravikumar obtained a Ph.D. in Computer Engineering from the Department of EE-Systems at University of Southern California (1991). He obtained an M.E. in Computer Science from Indian Institute of Science (1987) with highest scores and a B.E. in Electronics from Bangalore University (U.V.C.E.,1983) with a Gold Medal for highest scores. He has published over 250 research papers in the areas of VLSI physical design, VLSI test, parallel processing, electronic design automation and embedded systems in peer-reviewed journals and conferences. He has won four best-paper awards in international conferences of the IEEE and one best paper award in the IETE Journal of Education. He is the author/coauthor/editor of 15 books in the areas of VLSI design and Embedded Systems. He holds 4 US patents in the area of VLSI Test. He is a Fellow of INAE and a senior member of IEEE.
He founded the IEEE CAS Bangalore Chapter and has served as its honorary secretary. He has served as the honorary secretary of VLSI Society of India for 8 years. He established the VLSI Design Test and Symposium (VDAT) in India and was the general chair of this event for 15 years. He has served on the committees of numerous conferences in various capacities such as Program Chair and General Chair. He has served on the editorial committees of several journals, including Journal of Electronic Testing – Theory and Applications (Springer) and Journal of Low Power Electronics (ASP). He has received an award from Zinnov foundation and a recognition from IESA for his work with Indian universities. He received the “Best Blogger” award from TI University Program (2014).
Tutorial-2
Tutorial Title: "Physical Verification and Validation of Digital Analog and Mixed-Signal Designs for SCL 180nm CMOS Technology"
Abstract:
Physical Verification and Validation of Digital Analog and Mixed-Signal Designs for SCL 180nm CMOS Technology: Procedures prior to physical verification for the designs using SCL 180nm Process: Silicon number placement, Seal-ring insertion & guidelines, IO Pad pitch requirements, Dummy cells placement, Usage of clock pads and powering up the chip in SCL 180nm process, IO pad ring establishment with and without cut-cells, Physical verification, Design Rule Checks (DRCs), Antenna Design Rule Checks, Layout vs Schematic (LVS), Parasitic extraction, Spice simulations closure for all PVT (Process, Voltage, Temperature) variations, Tapeout sign-off and submission, Packaging requirements, bond pad and bond wire rules, bonding diagram, checklist, etc.
Brief profile of organizer(s):
Leya Wels is a Project Engineer at C-DAC Bangalore, currently associated with the Secure Hardware and VLSI Design group. She possesses two years of industry experience and holds a Bachelor of Technology degree in Electronics and Communication Engineering from Rajagiri School of Engineering & Technology, Kochi. Her work has primarily focused on the automation of physical verification and validation processes for digital, analog, and mixed-signal designs targeting the SCL 180nm CMOS technology node. Additionally, she is involved in the physical design of digital IP cores.
Pranose J. Edavoor received the Bachelor’s degree in Electronics and Communication Engineering from Cochin University of Science and Technology, Kerala, India, in 2012, the Master’s degree in Very Large-Scale Integration (VLSI) from the National Institute of Technology Goa, India, in 2016, and the Ph.D. degree in Electrical and Electronics Engineering from the same institute in 2021. He is currently with the Centre for Development of Advanced Computing (C-DAC), Bangalore, where he is involved in the design and development of AI accelerators and RISC-V-based processor architectures. His research interests include digital design, FPGA and ASIC-based accelerators, processor architecture, wavelet transforms, and deep neural networks.
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